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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 297 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
5 to 2 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
1
0
HW1
HW0
0
0
R/W
R/W
Delay Cycles from RD, WEn Negation to Address,
CSn Negation
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS6AWCR
Bit Bit Name
Initial
Value R/W Description
31 to 13 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
12
11
SW1
SW0
0
0
R/W
R/W
Number of Delay Cycles from Address, CSn Assertion
to RD, WE Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles