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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 379 of 982
REJ09B0023-0400
T1
T2
High
CKIO
A25 to A0
CSn
WEn
RD/WR
RD
RD
D31 to D0
D31 to D0
RD/WR
BS
DACKn*
Read
Write
Note: * The waveform for DACKn is when active low is specified.
Figure 12.38 Byte-Selection RAM Basic Access Timing (BAS = 1)