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Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 940 of 982
REJ09B0023-0400
Trw T c1 Trwl Tr Trw
t
AD1
t
CSD1
t
AD1
t
AD1
t
RWD1
t
RWD1
t
RWD1
t
CSD1
t
AD1
t
AD1
t
AD1
CKIO
A25 to A0
CSn
RD/WR
A12/A11*
1
D31 to D0
t
RASD1
t
RASD1
RASU/L
Row address
WriteA
command
Column
address
t
CASD1
t
CASD1
CASU/L
t
BSD
t
BSD
(High)
BS
CKE
t
DQMD1
t
DQMD1
DQMxx
t
DACD
t
DACD
DACKn*
2
t
WDH2
t
WDD2
Note:
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Figure 25.28 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle)