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Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 633 of 982
REJ09B0023-0400
18.7.9 Conflict between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 18.77 shows the timing in this case.
Input capture
signal
Write signal
Address
Pφ
TCNT
TGR write cycle
T1
T2
M
TGR
M
TGR address
Figure 18.77 Conflict between TGR Write and Input Capture