3Com MSR 50 Network Router User Manual


  Open as PDF
of 2742
 
676 CHAPTER 45: CPOS INTERFACE CONFIGURATION COMMANDS
Different from the display controller cpos command, this command can display
the error and alarm information of lower-order paths and T1 frames.
Example # Display the status information of T1 channel 2 on interface CPOS 4/0.
<Sysname> display controller cpos 4/0 t1 2
Cpos4/0 current state : UP Frame-format SDH, multiplex AU-3, clock
master, loopback not set
Tx: J0: 0x01, J1: "NetEngine", C2: 0x02
Rx: J0: 0x01, J1: "NetEngine", C2: 0x02
Regenerator section:
Alarm: none
Error: 0 BIP, 0 SEF
Multiplex section:
Alarm: none
Error: 0 BIP, 0 REI
Higher order path(VC-3-2):
Alarm: none
Error: 0 BIP, 0 REI
Lower order path:
Alarm: none
Error: 4095 BIP, 2047 REI
Cpos4/0 CT1 2 is up
Frame-format ESF, clock master, loopback not set
T1 framer(2-1-1):
Alarm: none
Error: 4095 FERR, 79 AERR
Table 123 Description on the fields of the display controller cpos t1 command
Field Description
Cpos4/0 current state The current physical state of the CPOS interface
Frame-format SDH, multiplex
AU-3, clock master, loopback
not set
Physical layer information of the CPOS interface: the
framing format is set to SDH, AU-3 path is adopted, master
clock (internal clock signal) is used, and loopback is
disabled.
Tx: J0: 0x01, J1: “NetEngine”,
C2: 0x02
The sent overhead bytes.
Rx: J0: 0x01, J1: “NetEngine”,
C2: 0x02
The received overhead bytes.
Regenerator section Alarms and errors about the regeneration section.
Multiplex section Alarms and errors about the regeneration section.
Higher order path(VC-3-2) Alarm and error statistics about the higher-order path to
which the T1 channel belongs. VC-3-2 means the second
VC-3.
Lower order path Alarm and error statistics about the lower-order path.
Error Error statistics.
Cpos4/0 CT1 2 is up The current physical state of T1 channel 2 on interface
CPOS 4/0.
Frame-format ESF, clock master,
loopback not set
Information about the physical layer of the T1 channel: the
framing format is set to ESF, master clock (internal clock
signal) is used, loopback is disabled.