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Chapter 4 CPU Architecture
6.Instruction Overview
6. Instruction Overview
The FR60 family supports logic operation, bit operation and direct addressing instruction optimized
for embedded application as well as general RISC instruction system. Instruction-set list is shown
in the appendix. Since each instruction is 16-bit length (some instruction is 32-bit or 48-bit length), it
enables you to generate compact program code.
Instruction sets are grouped into the following a through f function groups.
■ Arithmetic Operation
This group consists of standard arithmetic operation instruction (addition, subtraction and
comparison) and shift instruction (logic shift and arithmetic shift). For addition and subtraction, the
operation with carry used for multiple word length operation and the operation useful for address
calculation without changing flag value are allowed.
In addition, it includes 32-bit x 32-bit and 16-bit x 16-bit multiplication instruction as well as 32-bit/
32-bit step division instruction.
It provides transfer instruction of immediate value which sets immediate value to register, and
transfer instruction between registers.
All arithmetic instructions are operated using general-purpose register and multiply & divide register
within CPU.
■ Load and Store
Load/store is the instruction to read and write to memory. This is also used for read and write to
peripheral functions (I/O) within chip.
Load and store consist of 3 type access lengths including byte, half-word and word. In addition to
general register-indirect memory addressing, some instructions allow register-indirect memory
addressing with displacement or with register increment/decrement.
■ Branch
This is the instruction for branch, call, interrupt and return. Branch instruction consists of
instructions with and without delay slot. For more information of branch instruction, see “Chapter 7
Branch Instruction (Page No.129)”.
■ Logical Operation and Bit Operation
Logical operation instruction allows the logical operation of AND, OR and EOR between general-
purpose registers or general-purpose register and memory (and I/O). Bit operation instruction
allows the direct operation of data of memory (and I/O). Memory addressing is general register
indirect.
■ Direct Addressing
Direct addressing instruction is the instruction to access between I/O and general-purpose register,
or between I/O and memory. By directly instructing I/O address rather than register indirect, it
enables high-speed and high-efficient access. Some instructions allow register-indirect memory
addressing with register increment/decrement.
■ Others
This is the instruction which executes flag setting, stack operation, sign extension and zero
extension within PS register. It provides the function entrance/exit which supports high-level
language, and register multi-load/store instruction.