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Chapter 2 MB91460 Rev.A/Rev.B Overview
2.Features
• 4 words (16 bytes) per set
• Variable capacity (4/2/1 kB)
• Lock function enabling programs to be resident
• Available as instruction RAM requiring no wait state when not used as an instruction cache
• Direct mapped I-cache
• Up to 16 kByte integrated
• Variable capacity (16/8/4/2/1 kB)
• Lock function enabling programs to be resident
2.3 Interrupt Controller
• A total of 17 external interrupt lines (1 nonmaskable interrupt pin, 8 normal interrupt pins, 8 interrupt pins
shared (with peripheral inputs for Wake Up from STOP mode, e.g. CAN RX)
• Interrupts from internal peripherals (128 interrupt vectors)
• Priority levels programmable for normal interrupt lines excluding the nonmaskable one (16 levels)
• Capable of using the normal interrupt and nonmaskable interrupt pins for Wake Up from STOP mode
2.4 Internal Data RAM
• Up to 64 kBytes integrated
• Zero wait state for read/write access
• Referenced as Data-RAM or D-RAM in this manual
2.5 Internal Instruction/Data RAM
• Up to 64 kBytes integrated
• Zero wait state for read/write access of instructions
• One wait state for read/write access of data
• Referenced as General-Purpose-RAM (GP-RAM) or I/D-RAM in this manual
2.6 Embedded Instruction/Data Memory
• Up to 4 MByte (Flash or Mask ROM)
• Programmable wait state for read/write access
• Flash/ROM security
2.7 External Bus Interface
• 8 chip select areas with individual area size, data bus width selection (8, 16, 32-bit) and wait
• Address bus up to 32 bit wide
• Programmable auto-wait function or external wait input (RDY)
• Basic bus cycles : 2 cycles
• Prefetch function
• Burst access function
2.8 DMA Controller
• Four transfer modes supported: single/block, burst, continuous transfer, and fly-by
• 5 channels (4 channels for external-to-external transfer)