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Chapter 31 External Bus
4.Endian and Bus Access
■ Halfword Access
Big endian mode Little endian mode
32-bit bus
width
(1)
D00
D31D31
AA
BB
WR0
WR1
BB
AA
-
-
D00
address : "0"
Internal External Control
Reg terminal terminal
(1)
D00
D31D31
AA
BB
WR0
WR1
BB
AA
-
-
D00
address : "0"
Internal External Control
Reg terminal terminal
(1)
D00
D31D31
CC
DD
WR2
WR3
DD
CC
-
-
D00
address : "2"
Internal External Control
Reg terminal terminal
(1)
D00
D31D31
CC
DD
WR2
WR3
DD
CC
-
-
D00
address : "2"
Internal External Control
Reg terminal terminal