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Chapter 13 Clock Control
8.Caution
8. Caution
• Operation is not guaranteed if the clock source selection, main PLL multiplier setting, and division ratio
setting result in a frequency that exceeds the maximum.
• Take care with the sequence in which you set or modify the clock source selection.
• When the main clock oscillation is set to halt during subclock mode (OSCDS1 = “1”), selecting the main
clock (CLKS[1:0])=“00”, “01”, or “10”) is prohibited. To select the main clock, set (OSCDS1=“0”) and then
change to the main clock after waiting for the main clock oscillation to stabilize. Use the main clock
oscillation stabilization wait timer to provide the wait time. See “Chapter 22 Main Oscillation Stabilisation
Timer (Page No.289)” for details.
• When the sub clock oscillation is set to halt during subclock mode (OSCDS2 = “1”), selecting the sub clock
(CSVCR.SCKS=“0”) is prohibited. To select the sub clock, set (OSCDS2=“0”) and then change to the sub
clock after waiting for the sub clock oscillation to stabilize. Use the sub clock oscillation stabilization wait
timer to provide the wait time. See “Chapter 23 Sub Oscillation Stabilisation Timer (Page No.299)” for
details.
• When the main clock oscillation is halted (OSCDS1 = “1”) or the sub clock oscillation is halted (OSCDS2 =
“1”) an oscillation stabilization wait time (for main clock or subclock) is also required if a reset (INIT) occurs
that switches the clock source to the main clock. In this case, operation after the reset is not guaranteed if
the wait time set in the oscillation stabilization time selection bits (STCR.OS[1:0]) does not satisfy the
oscillation stabilization time requirement for the main clock.
Always set the oscillation stabilization time selection bits (STCR.OS[1:0]) to a value that provides an
adequate oscillation stabilization time for the main clock.
In the case of an INIT reset triggered by the INIT pin, the “L” level input must be maintained for long enough
for the main clock oscillation to stabilize.
See “Chapter 18 Timebase Counter (Page No.249)” and “Chapter 22 Main Oscillation Stabilisation Timer
(Page No.289)” for details of the oscillation stabilization wait.
• When changing to stop mode, the main PLL must either be halted or de-selected. Either set the main clock
oscillation halt bit (STCR.OSCD1 = “1”) to halt automatically or change the operating clock to main clock
divided by two before changing to stop mode.