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Chapter 7 Branch Instruction
5.Branch Instruction without Delay Slot
5. Branch Instruction without Delay Slot
• Branch instruction without delay slot:
6. Operation of Branch Instruction without Delay Slot
Operation without delay slot executes instructions in the order of instructions and never executes
the instruction located in the next address where a branch instruction exists before branch.
• Example
The number of execution cycles of branch instruction without delay slot is 2 cycles for branch and 1
cycle for no branch.
Unlike the branch instruction with delay slot where NOP is described because appropriate
instruction cannot be entered, it can increase efficiency of instruction code.
Select the operation with delay slot when valid instruction can be set in delay slot. Otherwise select
the operation without delay slot. This selection enables FR60 to satisfy both of execution rate and
code efficiency.
JMP @Ri CALL label12 CALL @Ri RET
BRA label9 BNO label9 BEQ label9 BNE label9
BC label9 BNC label9 BN label9 BP label9
BV label9 BNV label9 BLT label9 BGE label9
BLE label9 BGT label9 BLS label9 BHI label9
; Sequence of instruction
ADD R1
R2 ;
BRA:D LABEL ; Branch instruction (without delay slot)
MOV R2
R3 ; Not to be executed.
...
LABEL ST R3
@R4 ; Branched instruction