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Chapter 26 DMA Controller
3.DMA Controller (DMAC) Operation
● Fly-by transfer (I/O --> memory)
The DMA controller operates using a write operation as its unit of operation.
Otherwise, operation is the same as fly-by transfer (memory --> I/O) operation.
Access areas used for MB91460 series fly-by transfer must be external areas.
■ Transfer Address
The following types of addressing are available and can be set independently for each channel transfer source
and transfer destination.
The method for specifying the address setting register (DMASA/DMADA) for a 2-cycle transfer and the method
for a fly-by transfer are different.
● Specifying the address for a 2-cycle transfer
The value read from a register (DMASA/DMADA) in which an address has been set in advance is used as the
address for access. After receiving a transfer request, DMA stores the address from the register in the temporary
storage buffer and then starts transfer.
After each transfer (access) operation, the next access address is generated (increment/decrement/fixed
selectable) by the address counter and then written to the temporary storage buffer. Because the contents of the
temporary storage buffer are written back to the register (DMASA/DMADA) after each block transfer unit is
completed, the address register (DMASA/DMADA) value is updated after each block transfer unit is completed,
making it impossible to determine the address in real time during transfer.
● Specifying the address for a fly-by transfer
In a fly-by transfer, the value read from the transfer destination address register (DMADA) is used as the address
for access. The transfer source address register (DMASA) is ignored. Be sure to specify an external area as the
address to be set.
After receiving a transfer request, DMA stores the address from the register in the temporary storage buffer and
then starts transfer.
After each transfer (access) operation, the next access address is generated (increment/decrement/fixed
selectable) by the address counter and then written to the temporary storage buffer. Because the contents of this
temporary storage buffer are written back to the register (DMADA) after each block transfer unit is completed, the
address register (DMADA) value is updated after each block transfer unit is completed, making it impossible to
determine the address in real time during transfer.
■ Transfer Count and Transfer End
● Transfer count
The transfer count register is decremented (-1) after each block transfer unit is completed. When the transfer
count register becomes 0, counting for the specified transfer ends, and the transfer stops with the end code
displayed or is reactivated *.
Like the address register, the transfer count register value is updated only after each block transfer unit.
*: If transfer count register reloading is disabled, the transfer ends. If reloading is enabled, the register value is
initialized and then waits for transfer (DTCR of DMACB)
● Transfer end
Listed below are the sources for transfer end. When transfer ends, a source is indicated as the end code
(DSS[2:0] of DMACB).