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Chapter 14 PLL Interface
6.Clock Auto Gear Up/Down
6. Clock Auto Gear Up/Down
To avoid voltage drops and surges when switching the clock source from oscillator to high frequency PLL/
DLL output (or vice versa), a clock smooth gear-up and gear-down circuitry is implemented with the PLL
interface.
The main functionality is implemented using two divide-by counters (divide-by-M and divide-by-G
counter), where one supplies the PLL feedback always with the target frequency (divide-by-M counter),
and the other (divide-by-G counter) which increases the frequency from a programmable frequency divi-
sion given by the divide-by-G setting (DIVG) up to the target frequency given by the divide-by-M setting
(DIVM), or decreases the frequency from the divide-by-M setting (DIVM) down to the programmable end
frequency (DIVG).
In this sense only a setting of DIVG > DIVM is a valid clock gear specification to scale the system clock
from slower frequencies to faster frequencies (when gearing up) and from faster frequencies to slower
ones (when gearing down).
The frequency steps are performed in multiple of the PLL output frequency, e,g, the setting of: Oscillator
= 4 MHz, M = 2, N = 20 (which is a frequency multiplication of M * N = 40 with PLL output = 160 MHz
and frequency output to C-Unit = 80 MHz).
The gear divider can be set to any even divider, in this example it is G = 20, which causes the following
gear-up when switching from oscillator to PLL:
1. step : 1 cycle of 8.0 MHz (8.0 MHz equals 20 cycles of the PLL output)
2. step : 2 cycles of 8.4 MHz (8.4 MHz equals 19 cycles of the PLL output)
3. step : 3 cycles of 8.8 MHz (8.8 MHz equals 18 cycles of the PLL output)
:
17. step : 17 cycles of 40.0 MHz (40.0 MHz equals 4 cycles of the PLL output)
18. step : 18 cycles of 53.3 MHz (53.3 MHz equals 3 cycles of the PLL output)
19. step : 19 cycles of 80.0 MHz (80.0 MHz equals 2 cycles of the PLL output)
-> Target frequency reached by transition to last step (here from 18. to 19.)
Each step can be multiplied by setting a multiplication value in the gear multiplier register. The duration
from generating the start frequency up to reaching the target frequency can be calculated by the following
formula:
duration mul t k i k– 1+()⋅
k1=
i
∑
kik– 1+()⋅
kj1+=
i
∑
–
⎝⎠
⎜⎟
⎛⎞
⋅⋅=