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Chapter 33 I2C Controller
3.I2C Interface Operation
3. I
2
C Interface Operation
The I
2
C bus executes communication using two bi-directional bus lines, the serial data line (SDA) and serial
clock line (SCL). The I
2
C interface has two open-drain I/O pins (SDA/SCL) corresponding to these lines,
enabling wired logic applications.
■ Start Conditions
When the bus is free (BB=‘0’ in IBSR0, MSS=‘0’ in IBCR2), writing ‘1’ to the MSS bit places the I
2
C interface in
master mode and generates a start condition.
If a ‘1’ is written to it while the bus is idle (MSS=‘0’ and BB=‘0’), a start condition is generated and the contents
of the IDAR0 register (which should be address data) is sent.
Repeated start conditions can be generated by writing ‘1’ to the SCC bit when in bus master mode and
interrupt status (MSS=‘1’ and INT=‘1’ in IBCR0).
If a ‘1’ is written to the MSS bit while the bus is in use (BB=‘1’ and TRX=‘0’ in IBSR0; MSS=‘0’and INT=‘0’in
IBCR0), the interface waits until the bus is free and then starts sending.
If the interface is addressed as slave with write access (data reception) in the meantime, it will start sending
after the transfer ended and the bus is free again. If the interface is sending data as slave in the meantime, it
will not start sending data if the bus of free again. It is important to check whether the interface was addressed
as slave (MSS=‘0’ in IBCR0 and AAS=‘1’ in IBSR0), sent the data byte successfully (MSS=‘1’ in IBCR0) or
failed to send the data byte (AL=‘1’ in IBSR0) at the next interrupt!
Writing ‘1’ to the MSS bit or SCC bit in any other situation has no significance.
■ Stop Conditions
Writing ‘0’ to the MSS bit in master mode (MSS=‘1’ and INT=‘1’ in IBCR0) generates a stop condition and
places the device in slave mode. Writing ‘0’ to the MSS bit in any other situation has no significance.
After clearing the MSS bit, the interface tries to generate a stop condition which might fail if another master
pulls the SCL line low before the stop condition has been generated. This will generate an interrupt after the
next byte has been transferred!
■ Slave Address Detection
In slave mode, after a start condition is generated the BB is set to ‘1’ and data sent from the master device is
received into the IDAR0 register.
After the reception of eight bits, the contents of the IDAR2 register is compared to the ISBA register using the
bit mask stored in ISMK0 if the ENSB bit in the ISMK0 register is ‘1’. If a match results, the AAS bit is set to ‘1’
and an acknowledge signal is sent to the master. Then bit 0 of the received data (bit 0 of the IDAR0 register)
is inverted and stored in the TRX bit.
If the ENTB bit in the ITMK0 register is ‘1’ and a ten bit address header (11110, TA1, TA0, write access) is
detected, the interface sends an acknowledge signal to the master and stores the inverted last data bit in the
TRX register. No interrupt is generated. Then, the next transferred byte is compared (using the bit mask stored
in ITMK0) to the lower byte of the ITBA0 register. If a match is found, an acknowledge signal is sent to the
master, the AAS bit is set and an interrupt is generated.
If the interface was addressed as slave and detects a repeated start condition, the AAS bit is set after
reception of the ten bit address header (11110, TA1, TA0, read access) and an interrupt is generated.
Since there are seperate registers for the ten and seven bit address and their bitmasks, it is possible to make
the interface acknowledge on both addresses by setting the ENSB (in ISMK0) and ENTB (in ITMK0) bits. The
received slave address length (seven or ten bit) may be determined by reading the RAL bit in the ITMK0
register (this bit is valid if the AAS bit is set only).
It is also possible to give the interface no slave address by setting both bits to ‘0’ if it is only used as a master.
All slave address bits may be masked with their corresponding mask register (ITMK0 or ISMK0).