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Chapter 47 LCD Controller
8.Caution
8. Caution
• To access VRAM, be sure to use byte-by-byte access.
• Switching the frame period generation clocks:
Frame period generation clocks (LCR0:CSS) can be switched even during LCD display. However, switching
may cause some screen flicker. To avoid such flicker, be sure to set the blanking select bit (LCR0:BK) to “1”
(blank display) before switching.
• Depending on your LCD, different external divided resistors are used. Use appropriate resistor values.
• When the display mode is set to 1/2 duty cycle, non-selected waveform is output through the COM2 and
COM3 pins. For 1/3 duty cycle, the COM3 pin is used to output non-selected waveform.
• Inappropriate selection or setting of frame period generation clock (CSS), LCD drive power supply control
(VSEL), duty cycle (MS[1:0]) and frame period (FP[1:0]) results in inappropriate LCD display.
• LCD display is disabled in the main stop mode. To enable LCD display in the stop mode, use the sub-stop
mode. (See 6 “Setting procedure”.)