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Chapter 26 DMA Controller
3.DMA Controller (DMAC) Operation
■ Features of the Address Register
This register has the maximum 32-bit length. With 32-bit length, all space in the memory map can be accessed.
■ Function of the Address Register
• The address register is read in each access operation and the read value is sent to the address bus.
• At the same time, the address for the next access is calculated by the address counter and the address
register is updated using the calculated address.
• For address calculation, increment or decrement is selected independently for each channel, transfer
destination, and transfer source. The address increment/decrement width is specified by the address count
size register (SASZ/DASZ of DMACB).
• If reloading is not enabled, the address resulting from the address calculation of the last address remains in
the address register when the transfer ends.
• If reloading is enabled, the initial value of the address is reloaded.
Notes:
• If an overflow or underflow occurs as a result of 32-bit length full address calculation, an address error is
detected and transfer on the relevant channel is stopped. Refer to the description for the items related to the
end code.
• Do not set any of the DMAC’s registers as the address register.
• For demand transfer, be sure to set an address in an external area for the transfer source, transfer
destination, or both.
• Do not let the DMAC transfer data to any of the DMAC’s registers.
3.5 Data Types
Select the data length (data width) transferred in one transfer operation from the following:
• Byte
• Halfword
• Word
■ Data Length (Data width)
Since the word boundary specification is also observed in DMA transfer, different low-order bits are ignored if an
address with a different data length is specified for the transfer destination/transfer source address.
• Byte: The actual access address and the addressing match.
• Halfword: The actual access address has 2-byte length starting with 0 as the lowest-order bit.
• Word: The actual access address has a 4-byte length starting with 00 as the lowest-order 2 bits.
If the lowest-order bits in the transfer source address and transfer destination address are different, the
addresses as set are output on the internal address bus. However, each transfer target on the bus is accessed
after the addresses are corrected according to the above rules.
3.6 Transfer Count Control
Specify the transfer count within the range of the maximum 16-bit length (1 to 65536).