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Chapter 49 Real-Time Clock
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Figure 3-2 Register List
Note: For ICR registers and interrupt vectors, refer to “Chapter 24 Interrupt Control (Page No.311)”.
21 Bit Counter
INTE1WTCR: bit11
0
1
WTBR
WTSR
(W)
WTMR
(W)
WTHR
(W)
INT1 WTCR: bit10
0
1
Read: 1=
INT2 WTCR: bit12
0
1
Read: 1=
INTE2WTCR: bit13
0
1
INT3 WTCR: bit14
0
1
Read: 1=
INTE3WTCR: bit15
0
1
Disable interrupts
Enable interrupts
RTC
interrupt
(#132)
Overflow
INT4
WTCER: bit0
0
1
INTE4
WTCER: bit9
0
1
Disable interrupts
Enable interrupts
Every half second
Every minute
Every 24 hour (Everyday)
Every hour
Second Minute Hour
ST WTCR: bit 0
0
1
OR
0
1
1
1
1
0
0
0
WTBR value = 1/2 second
(Initial value indeterminate)
UPDT
0
1
WTCR: bit 2
No impact on operation
Update
RUN WTCR: bit 3
0
Read
RTC
1 RTC
Real-Time Clock
Overflow
Overflow
WTSR
(R)
WTMR
(R)
WTHR
(R)
OR
Prescaler: 1/2
INTE1WTCR: bit11
0
1
INTE1WTCR: bit11
0
1
Disable interrupts
Enable interrupts
Reload
Second Counter
Minute Counter
Hour Counter
INT1 WTCR: bit10
0
1
Read: 1=
INT1 WTCR: bit10
0
1
Disable
Read: 1=Interrupt request has been made
Read: 1=Interrupt request has been made
INT2 WTCR: bit12
0
1
Read: 1=
INT2 WTCR: bit12
0
1
Disable
Disable
INTE2WTCR: bit13
0
1
INTE2WTCR: bit13
0
1
Disable interrupts
Enable interrupts
INT3 WTCR: bit14
0
1
Read: 1=
INT3 WTCR: bit14
0
1
Clear interrupt requests
Clear interrupt requests
Clear interrupt requests
Clear interrupt requests
Disable
ST WTCR: bit 0
0
1
ST WTCR: bit 0
0
1
Stop after reset
Start
0
1
RUN WTCR: bit 3
0
Read
RTC
1 RTC
RUN WTCR: bit 3
0
Read only
RTC inactive
1 RTC active
Read: 1=Interrupt request has been made
Read: 1=Interrupt request has been made
OR
INT0 WTCR: bit8
0
1
INTE0 WTCR: bit9
0
1
Disable interrupts
Enable interrupts
Every second
0
1
Read: 1=Interrupt request has been made
Disable
Clear interrupt requests
Oscillation