Fujitsu FR60 Computer Hardware User Manual


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Chapter 41 Up/Down Counter
8.Caution
8. Caution
The count direction is set to “countdown” immediately after resetting the counter. So, when the counter
counts up immediately after resetting, the count direction change bit (UDCC.CDCF) is set to “1” to indicate a
direction change has been made.
When the up/down counter register UDCR has reached the maximum count, the overflow flag is set to 1 and
counting continues. This time UDCR is cleared.
The minimum pulse width for AIN, BIN and ZIN signals is 2xT (T=1/CLKP: Period of a peripheral clock)
If you determine whether a change has been made to the count direction change interrupt and count
direction flags, you must take it into consideration that when several direction changes have been made
continuously in a short period of time, the count direction flag may be returned to the original value, which
looks as if no change has been made.
The compare detection flag (UDCS.CMPF) is set to “1” when Up/Down Counter's count value agrees with
the compare value during both counting up and down. These flags are also set to 1 when:
The reload value is reloaded to Up/Down Counter; or
The Up/Down Counter's count value agrees with the compare value when Up/Down Counter is activated.
The Up/Down Counter's count value is cleared by a clear request which is generated:
On the edge of a signal input from the ZIN pin;
By writing “0” to the up/down counter clear bit (UDCC.UDCLR); or
When the compare value agrees with the count value.
In addition,
On reset input (INITX, RST and watchdog reset); or
When the counter counts up from the maximum account,
the count value is also set to “0000
H
”.
When Up/Down Counter clear and reload requests are made at the same time, the former takes precedence
over the latter.
When Up/Down Counter is counting up, writing to the counter is disabled.
{Writing “1” to the counter write bit (UDCC.CTUT) after writing to the UDRC register is disabled.}
Should the software perform a reload operation during counting, the reload takes precedence and the event
that should have taken place no longer occurs.
The software cannot clear the up/down flags (UDCS.UDF[1:0]) to “0”. Only reset (initialization) can clear the
flag to “0”.