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Chapter 34 CAN Controller
2.Register Description
■ Function of the Status Register (STATR)
[bit15 - bit8] Reserved Bits
[bit7] BOff Busoff Status
0 The CAN module is not busoff.
1 The CAN module is in busoff state.
[bit6] EWarn Warning Status
0 oth error counters are below the error warning limit of 96.
1 At least one of the error counters in the EML has reached the error warning limit
of 96.
[bit5] EPass Error Passive
0 The CAN Core is error active.
1 The CAN Core is in the error passive state as defined in the CANSpecification.
[bit4] RxOk Received a Message Successfully
0 Since this bit was last reset by the CPU, no message has been successfully
received. This bit is never reset by the CAN Core.
1 Since this bit was last reset (to zero) by the CPU, a message has been success-
fully received (independent of the result of acceptance)
[bit3] TxOk Transmitted a Message Successfully
0 Since this bit was reset by the CPU, no message has been successfully trans-
mitted. This bit is never reset by the CAN Core.
1 Since this bit was last reset by the CPU, a message has been successfully (error
free and acknowledged by at least one other node) transmitted.
[bit2 - bit0] LEC Last Error Code (Type of the last error to occur on the CAN bus)
0 No Error
1
Stuff Error
More than 5 equal bits in a sequence have occurred in a part of a
received message where this is not allowed.
2 Form Error A fixed format part of a received frame has the wrong format.
3
AckError
The message this CAN Core transmitted was not acknowledged by
another node.
4
Bit1Error
During the transmission of a message (with the exception of the arbi-
tration field), the device wanted to send a recessive level (bit of logi-
cal value ‘1’), but the monitored bus value was dominant.