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Chapter 31 External Bus
2.External Bus Interface Registers
Table 4.2 - 22 lists the settings for the write recovery cycle.
For all the areas connected to SDRAM/FCRAM, set these bits to the same write recovery cycle.
[Bits 3 - 2] W03 and W02 (RAS Active time): RAS active time
Set these bits to the minimum number of cycles for RAS active time.
Table 4.2 - 23 lists the settings for RAS active time.
For all the areas connected to SDRAM/FCRAM, set these bits to the same RAS active time.
[Bits 1 - 0] W01 and W00 (RAS precharge cycle): RAS precharge cycles
Set these bits to the number of RAS precharge cycles.
Table 4.2 - 24 lists the settings for the RAS precharge cycle.
For all the areas connected to SDRAM/FCRAM, set these bits to the same RAS precharge cycle.
2.4 Memory setting register (MCRA for SDRAM/FCRAM auto - precharge OFF mode)
This section describes the configuration and the function of memory setting register (MCRA for
SDRAM/FCRAM auto - precharge OFF mode).
Table 2-13 Write recovery cycle
W05 W04 Write recovery cycle
0 0 Prohibited
0 1 2 cycles
1 0 3 cycles
1 1 4 cycles
Table 2-14 RAS active time
W03 W02 RAS active time
0 0 1 cycle
0 1 2 cycles
1 0 5 cycles
1 1 6 cycles
Table 2-15 RAS precharge cycle
W03 W02 RAS precharge cycle
0 0 1 cycle
0 1 2 cycles
1 0 3 cycles
1 1 4 cycles