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Chapter 12 Instruction Cache
2.Main body structure
[Bit 7] RAM: RAM Mode
Setting this bit to "1" causes the cache to operate in RAM mode. By placing the cache in RAM
mode, the cache RAM is mapped as shown in Figure I-CACHE-3 while the cache is enabled
with the ENAB bit set to "1".
[Bit 5] GBLK: Global lock bit
This bit locks all of the current entries in the cache. Setting the GBLK bit to "1" prevents the
valid entries in the cache from being updated when a cache miss occurs. Note, however, that
invalid sub-blocks are updated then. Fetching of instruction data in the global lock state is
performed in the same way as not in that state.
[Bit 4] ALFL: Auto lock fail bit
This bit (ALFL) is set to 1 if locking is attempted on an entry that is already locked. If, during
entry autolock, an entry update is attempted on an entry that is already locked, no new entry
is locked in the instruction cache regardless of what the user intends. Reference this bit for
debugging of a program or similar purpose. Clear this bit by writing 0 to it.
[Bit 3] EOLK: Entry auto lock bit
This bit enables or disables auto-locking for each entry in the instruction cache. An entry
accessed (but resulting in a miss) with the EOLK bit containing "1" is locked when the entry
lock bit in the cache tag is set to "1" by hardware. Once locked, the entry is not updated at
any cache miss that follows until it is unlocked. Note, however, that invalid sub-blocks are
updated. To ensure the entry lock, set this bit after flushing.
[Bit 2] ELKR: Entry lock release bit
This bit specifies the clearing of the entry lock bits in all cache tags. When the ELKR bit is set
to "1" in a cycle, the entry lock bits in all cache tags are cleared to "0" in the next cycle. Note
that the content of this bit is retained for only one clock cycle; it is cleared to "0" in the clock
cycle that follows.
[Bit 1] FLUSH: Flush bit
This bit specifies the flushing of the instruction cache. Setting the FLUSH bit to "1" flushes the
cache. Note that the content of this bit is retained for only one clock cycle; it is cleared to "0"
in the clock cycle that follows.
[Bit 0] ENAB:Enable bit
This bit enables or disables the instruction cache. Setting the ENAB bit to "0" disables the
cache, where the CPU directly accesses external memory to request instructions without
cache intervention. While disabled, the cache retains its contents.