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Chapter 34 CAN Controller
4.CAN Application
4. CAN Application
This section describes how to use the CAN module in the application
4.1 Management of Message Objects
The configuration of the Message Objects in the Message RAM will (with the exception of the bits MsgVal,
NewDat, IntPnd, and TxRqst) not be affected by resetting the chip. All the Message Objects must be
initialized by the CPU or they must be not valid (MsgVal = ‘0’) and the bit timing must be configured before the
CPU clears the Init bit in the CAN Control Register.
The configuration of a Message Object is done by programming Mask, Arbitration, Control and Data field of
one of the two interface register sets to the desired values. By writing to the corresponding IFx Command
Request Register, the IFx Message Buffer Registers are loaded into the addressed Message Object in the
Message RAM.
When the Init bit in the CAN Control Register is cleared, the CAN Protocol Controller state machine of the
CAN_Core and the Message Handler State Machine control the CAN’s internal data flow. Received messages
that pass the acceptance filtering are stored into the Message RAM, messages with pending transmission
request are loaded into the CAN_Core’s Shift Register and are transmitted via the CAN bus.
The CPU reads received messages and updates messages to be transmitted via the IFx Interface Registers.
Depending on the configuration, the CPU is interrupted on certain CAN message and CAN error events.
4.2 Message Handler State Machine
The Message Handler controls the data transfer between the Rx/Tx Shift Register of the CAN Core, the
Message RAM and the IFx Registers.
• The Message Handler FSM controls the following functions:
• Data Transfer from IFx Registers to the Message RAM
• Data Transfer from Message RAM to the IFx Registers
• Data Transfer from Shift Register to the Message RAM
• Data Transfer from Message RAM to Shift Register
• Data Transfer from Shift Register to the Acceptance Filtering unit
• Scanning of Message RAM for a matching Message Object
• Handling ofTxRqst flags.
• Handling of interrupts.
4.3 Data Transfer from/to Message RAM
When the CPU initiates a data transfer between the IFx Registers and Message RAM, the Message Handler
sets an internal busy signal which delays a consecutive access. After the transfer has completed, the busy
signal is set back and the consecutive access is executed.
The respective Command Mask Register specifies whether a complete Message Object or only parts of it will
be transferred. Due to the structure of the Message RAM it is not possible to write single bits/bytes of one
Message Object, it is always necessary to write a complete Message Object into the Message RAM.
Therefore the data transfer from the IFx Registers to the Message RAM requires a read-modify-write cycle.
First parts of the Message Object that are not to be changes are read from the Message RAM and then the
complete contents of the Message Buffer Registers are written into the Message Object.