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Chapter 34 CAN Controller
2.Register Description
■ Function of the CAN Control Register (CTRLR)
(Note) The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or
resetting Init. If the device goes busoff, it will set Init of its own accord, stopping all bus activities.
Once Init has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle
(129 * 11 consecutive recessive bits) before resuming normal operations. At the end of the busoff
[bit15 - bit8] Reserved Bits
[bit7] Test Test Mode Enable
0 Normal Operation.
1 Test Mode.
[bit6] CCE Configuration Change Enable
0 The CPU has no write access to the Bit Timing Register.
1 The CPU has write access to the Bit Timing Register (while Init = 1)
[bit5] DAR Disable Automatic Retransmission
0 Automatic Retransmission of disturbed messages enabled.
1 Automatic Retransmission disabled.
[bit4] res reserved bit
[bit3] EIE Error Interrupt Enable
0 Disabled - No Error Status Interrupt will be generated.
1 Enabled - A change in the bits BOff or EWarn in the Status Register will generate
an interrupt.
[bit2] SIE Status Change Interrupt Enable
0 Disabled - No Status Change Interrupt will be generated.
1 Enabled - An interrupt will be generated when a message transfer is successfully
completed or a CAN bus error is detected.
[bit1] IE Module Interrupt Enable
0 Disabled - Module Interrupt is always inactive.
1 Enabled - Interrupts will set the internal request. The request remains active until
all pending interrupts are processed.
[bit0] Init Initialization
0 Normal Operation
1 Initialization is started.