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Chapter 1 Introduction
2.Instruction for Users
■ Caution: PS register
Because some commands previously proceed PS register, interrupt processing routine may be broken during
the use of debugger or displayed data on PS flag may be updated due to the following excecptional operations
((1) and (2)).
In each case, it is designed to correctly re-proceed operations after the return, the operation before and after
EIT is carried out in accordance with the specification.
• In immediately preceding DIV0U or DIV0S command,
• If interrupted by user,
• If stepwise execution is carried out,
• If data event or emulator menu made a break,
The following operation may be generated.
1. D0 or D1 flag is updated ahead.
2. EIT processing routine (interruption by user or emulator) is carried out.
3. After the return from EIT, it executes DIV0U or DIV0S command and then D0 or D1 flag are updated
to the same value as 1.
• If you execute each command of ORCCR, STILM, MOV Ri or PS to enable interruption with
interruption by user generated, the following operation may be generated.
4. PS register is updated ahead.
5. EIT processing routine (interruption by user) is carried out.
6. After the return from EIT, it executes commands above, and then PS register is updated to the same
value as 1.
■ Watchdog timer function
Watchdog timer function equipped with FR60 monitors the progress to ensure that program executes reset
delay operation within a specified time and resets CPU if reset delay operation was not executed due to
runaway of program. Once you enable watchdog timer function, it continues running until it is reset.
By way of exception, reset delay is automatically conducted under the condition where CPU program
execution is stopped. For this exceptional condition, see “Chapter 20 Software Watchdog Timer (Page
No.273)“.
■ Register against read/modify/write command
SMR register within UART cannot use read/modify/write command. To write in SMR register, write by Byte/
Half-word/Word in consideration with write control bit (bit-5, 4, 2, 0) rather than accessing by bit-by-bit.