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Chapter 7 Branch Instruction
4.Restrictions on Branch Instruction with Delay Slot
4. Restrictions on Branch Instruction with Delay Slot
4.1 Available Instructions for Delay Slot
Instructions which meet the following requirements can only be executed in delay slot.
• 1-cycle instruction
• Non-branch instruction
• Instruction which does not affect any operation even if its sequence is changed.
“1-cycle instruction” indicates instructions whose number of cycles column in the instruction list table is
described with “1”, “a”, “b”, “c” or “d”.
4.2 Step Trace Trap
Step trace trap is not generated between the execution of branch instruction with delay slot and delay slot.
4.3 Interrupt
Interrupt is not acceptable between the execution of branch instruction with delay slot and delay slot.
4.4 Undefined-instruction Exception
If undefined instruction exists in delay slot, undefined instruction-exception is not generated. In this case,
undefined instruction works as NOP instruction.