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Chapter 33 I2C Controller
2.I2C Interface Registers
[bit 14] BEIE (Bus Error Interrupt Enable)
This bit enables the bus error interrupt. It can only be changed by the user.
Setting this bit to ‘1’ enables MCU interrupt generation when the BER bit is set to ‘1’.
[bit 13] SCC (Start Condition Continue)
This bit is used to generate a repeated start condition. It is write only - it always reads ‘0’.
A repeated start condition is generated if a ‘1’ is written to this bit while an interrupt in master mode (MSS=‘1’
and INT=‘1’) and the INT bit is cleared automatically.
[bit 12] MSS (Master Slave Select)
This is the master/slave mode selection bit. It can only be set by the user, but it can be cleared by the user
and the hardware.
It is cleared if an arbitration loss event occurs during master sending.
If a ‘0’ is written to it during a master interrupt (MSS=‘1’ and INT=‘1’), the INT bit is cleared automatically, a
stop condition will be generated and the data transfer ends. Note that the MSS bit is reset immediately, the
generation of the stop condition can be checked by polling the BB bit in the IBSR0 register.
If a ‘1’ is written to it while the bus is idle (MSS=‘0’ and BB=‘0’), a start condition is generated and the contents
of the IDAR0 register (which should be address data) is sent.
If a ‘1’ is written to the MSS bit while the bus is in use (BB=‘1’ and TRX=‘0’ in IBSR2; MSS=‘0’ in IBCR0), the
interface waits until the bus is free and then starts sending.
If the interface is addressed as slave with write access (data reception) in the meantime, it will start sending
after the transfer ended and the bus is free again. If the interface is sending data as slave in the meantime
(AAS=‘1’ and TRX=‘1’ in IBSR0), it will not start sending data if the bus is free again. It is important to check
whether the interface was addressed as slave (AAS=‘1’ in IBSR0), sent the data byte successfully (MSS=‘1’ in
IBCR0) or failed to send the data byte (AL=‘1’ in IBSR0) at the next interrupt!
[bit 11] ACK (ACKnowledge)
This is the acknowledge generation on data byte reception enable bit. It can only be changed by the user.
0 Bus error interrupt disabled.
1 Bus error interrupt enabled.
0 No effect.
1 Generate repeated start condition during master transfer.
0 Go to slave mode.
1
Go to master mode, generate start condition and send address data byte in
IDAR0 register.
0 The interface will not acknowledge on data byte reception.
1 The interface will acknowledge on data byte reception.