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Chapter 34 CAN Controller
2.Register Description
Base-addr +
0x40
IF2 Command Request IF2 Command Mask
bit[15:8] bit[7:0] bit[15:8] bit[7:0]
Busy Mess. No. [5:0] reserved see descr. IF2CMSK
Reset: 0x00 Reset: 0x01 Reset: 0x00 Reset: 0x00
Base-addr +
0x44
IF2 Mask 2 IF2 Mask 1
bit[15:8] bit[7:0] bit[15:8] bit[7:0]
MXtd,MDir,Msk[28:24] Msk[23:16] Msk[15:8] Msk[7:0]
Reset: 0xFF Reset: 0xFF Reset: 0xFF Reset: 0xFF
Base-addr +
0x48
IF2 Arbitration 2 IF2 Arbitration 1
bit[15:8] bit[7:0] bit[15:8] bit[7:0]
MsgVal,Xtd,Dir,ID[28:24] ID[23:16] ID[15:8] ID[7:0]
Reset: 0x00 Reset: 0x00 Reset: 0x00 Reset: 0x00
Base-addr +
0x4C
IF2 Message Control Reserved
bit[15:8] bit[7:0] bit[7:0] bit[15:8]
see descr. IF2MCTR see descr. IF2MCTR reserved reserved
Reset: 0x00 Reset: 0x00 Reset: 0x00 Reset: 0x00
Base-addr +
0x50
IF2 Data A1 IF2 Data A2 Big Endian byte
ordering.
bit[7:0] bit[15:8] bit[7:0] bit[15:8]
Data[0] Data[1] Data[2] Data[3]
Reset: 0x00 Reset: 0x00 Reset: 0x00 Reset: 0x00
Base-addr +
0x54
IF2 Data B1 IF2 Data B2 Big Endian byte
ordering.
bit[7:0] bit[15:8] bit[7:0] bit[15:8]
Data[4] Data[5] Data[6] Data[7]
Reset: 0x00 Reset: 0x00 Reset: 0x00 Reset: 0x00
Base-addr +
0x60
IF2 Data A2 IF2 Data A1 Little Endian byte
ordering.
bit[15:8] bit[7:0] bit[15:8] bit[7:0]
Data[3] Data[2] Data[1] Data[0]
Reset: 0x00 Reset: 0x00 Reset: 0x00 Reset: 0x00
Base-addr +
0x64
IF2 Data B2 IF2 Data B1 Little Endian byte
ordering.
bit[15:8] bit[7:0] bit[15:8] bit[7:0]
Data[7] Data[6] Data[5] Data[4]
Reset: 0x00 Reset: 0x00 Reset: 0x00 Reset: 0x00
Address
Register
Note
+0 +1 +2 +3