Filter
Top Products
5
Chapter 1 Introduction
2.Instruction for Users
■ Caution: writing to registers which include a status flag
Writing to a register including a status flag (in particular, interrupt request flag) in order to control the function,
note that you should not clear status flag unintentionally.
That is, take care not to clear the flag for status bit and make control bit to be the expected value during the
writing.
Especially, for control bits consisting of several bits, bit command is not available since single bit access is
only acceptable for bit command, you should write into the both of control bit and status flag at the same time
by Byte/Half-word/Word access. In this case, you should not clear other bits (bits of status flag) unintentionally.
The following shows registers which mostly include both of several bits and status flag.
• TBCR
• OSCR
•TWCR
• TCCS0, TCCS1
• ICS01
• TMCSR0, TMCSR1, TMCSR2, TMCSR3
• PCN00, PCN01, PCN02,...
• ADCSL0, ADCSL1
• CCR0, CCR1
Note: For bit command, you do not have to be careful since this matter has been already considered.
■ Caution: writing to registers which include a status flag
Writing to a register including a status flag (in particular, interrupt request flag) in order to control the function,
note that the actual writing to the registers may be delayed. This is because of using write buffers on the
busses to the resources which accept a write access from CPU immediately but can access the resource
registers delayed.
In this case it can happen that within an ISR the interrupt request flag is cleared by writing to the register and
the ISR is completed with RETI, but the interrupt request flag is still active and the ISR is executed again.
To synchronize the access to the resources on this architecture please follow this recommendation:
Use a read access (byte or halfword) to the RBSYNC address to synchronize the CPU operation (e.g. the
interrupt acceptance of the CPU) to a preceding write access to the resources on R-bus (e.g. to an interrupt
flag) on following addresses (0x0000-0x01FF, 0x0280-0x037F, 0x0400-0x063F and 0x0C00-0x0FFF).
Use a read access (byte or halfword) to the CBSYNC address to synchronize the CPU operation (e.g. the
interrupt acceptance of the CPU) to a preceding write access to the CANs on D-bus (e.g. to an interrupt flag)
on following addresses (0xC000-0xFFFF).