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Chapter 48 Clock Monitor
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Figure 3-2 Register List
Clock Monitor
CMCFG
CMSEL3:0
0000
Disable clock monitor output
MONCLK
Internal clocks
Prescaler
Selector
Enable clock monitor output
Others
CMCFG
CMSEL3:0
0000
Disable clock monitor output
0001
0010
Main oscillation before CSV
Sub oscillation before CSV
0011
0100
RC oscillation
Sub clock (after SCKS)
0101
0110
Main oscillation after CSV
Sub oscillation after CSV
0111
1000
Clock modulator output to C-Unit
Clock modulator observer output
1001
PLL output after 1/g
1010
1011
PLL output after 1/m
PLL output after 1/c
1100
1101
PLL input after 1/n
CLKB
1110
1111
CLKP
CLKT
CMPRE3:0
Clock Output
Frequency
CMCFG bit 7-4
0
0
0
0
0
1
1
1
1
10
11
0
1
0
00
01
10
11
φ
φ
φ
φ
φ
φ
φ
φ
/1
/2
/6
/7
/8
/3
/4
/5
0
0
0
0
0
0
0
0
CMPRE3:0
Clock Output
Frequency
0
0
0
0
0
1
1
1
1
10
11
0
1
0
00
01
10
11
1
1
1
1
1
1
1
1
φ
φ
φ
φ
φ
φ
φ
φ
/9
/10
/14
/15
/16
/11
/12
/13