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Chapter 31 External Bus
9.SDRAM/FCRAM Interface Operation
■ Self Refresh
Writing 1 to the SELF bit in the refresh control register (RCR) causes the SDRAM/FCRAM interface to initiate the
self - refresh transition sequence.
After executing auto - refreshing the number of times set in the RFC2 to RFC0 bits, the SDRAM/FCRAM interface
issues the SELF command to SDRAM/FCRAM to enter the self - refresh mode.
The device is released from the self - refresh mode either when 0 is written to the SELF bit or read/write access
to SDRAM/FCRAM occurs.
The SDRAM/FCRAM interface issues the SELFX command to execute auto - refreshing the number of times set
in the RFC2 to RFC0 bits upon detection of writing 0 to the SELF bit or access to SDRAM/FCRAM in the self -
refresh mode.
Even when access to SDRAM/FCRAM by DMA transfer occurs after setting the self - refresh mode and putting
the chip into sleep mode, the self - refresh mode is canceled.
● Self - refresh mode transition procedure
1. Set SELF bit to "1".
2. Issue the REF command the number of times set in the RFC2 to RFC0 bits.
3. Issue SELF command
● Self - refresh mode reset procedure
1. Set the SELF bit to 0 or access to SDRAM/FCRAM.
2. Issue SELFX command
3. Issue the REF command the number of times set in the RFC2 to RFC0 bits.
4. Transition to the normal access state
9.2 Power-on Sequence
This section describes the power - on sequence.
■ Power-on Sequence
Setting the PON bit in the refresh control register (RCR) to 1 initiates the power - on sequence.
Take the following steps to set the PON bit to 1 for transition to the power - on sequence.
1. Reserve the clock stabilization wait time specified in the SDRAM/FCRAM manual.
2. Set ACR, AWR, MCRA(B).
3. Set the CSER to enable the area to which SDRAM/FCRAM has been connected.
4. Set the PON bit to 1 while setting the RCR value.
Taking the above steps causes the SDRAM/FCRAM interface to execute the following power - on sequence.
5. Execute the PALL command.
6. Execute the REF command eight times.
7. The mode register is set according to the BST bit in the ACR, CL (CAS Latency) bit in the AWR, and the
WBST bit in the MCRA.
8. Transition to the normal access state