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Chapter 5 CPU Registers
2.Dedicated Registers
This bit becomes “0” by reset.
• [Bit 3] N: Negative flag
This bit indicates the sign when operation results is deemed as integer represented by two’s-complement numbers.
• [Bit 2] Z: Zero flag
It indicates whether operation result is 0 or not.
• [Bit 1] V: Overflow flag
This bit deems that operand used for operation as integer represented by two’s-complement numbers, and indicates
whether overflow was generated or not as the result of operation results.
• [Bit 0] C: Carry flag
This bit indicates whether carry or borrow from highest-order bit was generated or not as the result of operation.
■ SCR: System Condition Code Register
Figure 2-5 Structure of System Condition Code Register (SCR)
This section describes each bit structure of system condition code register (SCR).
• [Bit 10, 9] D1 and D0: Step division flag
D1 and D0 bits hold intermediate data during the execution of step division.
Do not modify data during the execution of division processing.
If other processes is executed during the execution of step division, step division is assured to be restarted by saving
and returning PS register value.
Initial status by reset is indeterminate for D1 and D0 bits.
Upon executing DIV0S instruction, these bits are set by referring to dividend and divisor.
Upon executing DIV0U instruction, these bits mandatorily become “00”.
• [Bit 8] T: Step trace trap flag
This bit is the flag to specify whether to enable step trace trap or not.
This bit is initialized to “0” by reset.
The function of step trace trap is used for emulator. During the use of emulator, you cannot use this bit for user
N Description
0 It indicates that operation result is positive value.
1 It indicates that operation result is negative value.
Z Description
0 It indicates that operation result is other than 0.
1 It indicates that operation result is 0.
V Description
0 It indicates that overflow was not generated as the result of operation.
1 It indicates that overflow was generated as the result of operation.
Value Description
0 It indicates that neither carry nor borrow is generated.
1 It indicates that either carry or borrow is generated.
T value Description
0 Disables step trace trap.
1
Enables step trace trap.
In this case, all user interrupts are disabled.
10 9 8
[Initial value]
D1 D0 T XX0
B
SCR