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Chapter 48 Clock Monitor
8.Caution
8. Caution
Due to the glitch free switching mechanism it is necessary to follow these rules when switching the clock
source (CMCFG3:0) or the prescaler ratio (CMPRE3:0):
- The CMPRE3:0 registers can only be written if the CMCFG3:0 registers are currently 0x0.
- The CMPRE3:0 registers can only be written if the CMCFG3:0 registers are written to 0x0 within the same
write access.
- Between 2 write accesses to CMPRE/CMCFG there must be at least 2 cycles of the divided monitor clock.