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Chapter 31 External Bus
10.DMA Access Operation
If SDRAM access is shorter than I/O access, the SDRAM access is extended by the I/O access (base access
plus I/O wait).
Figure 4.10 - 5 shows an operation timing chart assuming TYP3 to TYP0 set to 1000B, AWR set to 0051H, and
IOWR set to 42H.
● At SDRAM page misses
Figure 10-5 Timing Chart for DMA Fly - by Transfer (SDRAM/FCRAM to I/O) with Page Misses
• If SDRAM access is extended, for example, by precharging when a page miss occurs in reference to SDRAM,
the SDRAM access exceeds the set I/O access, so that the I/O access is extended to be longer than the
SDRAM access. When the I/O device requires data setup, therefore, the I/O wait cycle must be set such that I/
O access is longer than the maximum SDRAM access cycle. For the above settings, set the number of I/O
wait cycles to at least 4.
• For SDRAM/FCRAM on the data output side, a READ command is issued at the timing that satisfies the I/O
wait cycle. If the I/O hold cycle has been set, then, a DESL command is issued to insert the I/O hold cycle in
the cycle immediately followed by the
Bank
address
IOWR
DACKn
DEOPn
DREQn
Basic
mode
MCLK
CSn
SCAS
A31 to 0
D31 to 0
WRn(SWE)
SRAS
I/O basic cycle
I/O wait
I/O hold
wait
MCLKE
SDRAM basic cycle
Row
address
Column
address