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Chapter 17 Clock Modulator
2.Clock Modulator Registers
In the Table below the modulator states are summarized:
bit 1 FMOD:
Frequency
modulation
enable bit
"0": Frequency modulation disabled.
"1": Frequency modulation enabled.
• To enable the modulator in frequency modulation mode, FMOD must be set to 1.
• Before the modulator can be enabled, the PLL must deliver a stable reference clock
(PLL lock time must be elapsed).
• The specified PLL frequency range for frequency modulation mode is 15 MHz to 25
MHz.
• Each PLL output frequency offers a set of possible modulation parameters. The
selected setting (CMPR register) and the PLL frequency must match.
Please refer to the CMPR register description.
• Whenever the PLL output frequency is changed or the PLL is switched off e.g. in
power down modes, the modulator must be disabled before -> FMOD=0 and
FMODRUN=0.
• Before the modulator can be enabled, it must be switched from power down to active
mode by setting PDX to 1. And the startup time of 6us must be awaited.
Please refer to the application note for a description of the recommended startup
sequence.
• Before the modulator can be enabled in frequency modulation mode, a proper setting
must be selected via the parameter register CMPR.
• After enabling the frequency modulation mode by setting FMOD to 1, the modulator
is calibrated. During this time, the clock is unmodulated. Therefore the output clock
does not switch immediately to modulated clock. The status of the clock (frequency
modulated / unmodulated) is indicated by the FMODRUN status bit. Please refer to
the FMODRUN bit description.
• Due to the synchronization of the FMOD signal and the synchronized switching to
unmodulated clock, it takes less than 9 x T0 (input clock period) before the clock
switches to unmodulated clock after the modulator is disabled. The modulator can be
disabled at any time.
• Before changing the parameter register CMPR, the modulator must be disabled ->
FMOD=0 and FMODRUN=0.
bit 0 PDX:
Power down bit
"0": Power down mode
"1": Power up
• PDX is the power down signal for the modulator. Before the frequency modulation
mode can be enabled, this bit must be set to 1 and the startup time of 6us must be
awaited. Please refer to the application note for a description of the recommended
startup sequence.
• Before switching to power down mode (PDX=0), the modulator must be disabled ->
FMOD=0 and FMODRUN=0.
Table 2-2 States of the modulator
FMOD PDX
FMODRUN
(read only)
modulator disabled 0 0 0
modulator power on,
waiting modulator startup time (> 6 us)
01 0
Table 2-1 Function of each bit of the clock modulator control register (2 / 2)
Bit name Function