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Chapter 23 Sub Oscillation Stabilisation Timer
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Figure 3-2 List of Registers
Note: For the ICR register and interrupt vector, refer to “Chapter 24 Interrupt Control (Page No.311)”.
01234567891011121314
Clock timer
Clock timer
(14-bit free run timer)
Sub-clock
(Source oscillation)
32.768 kHz
WCL WPCR:bit 2
0
1
Timer clear
Does not affect the operation
Timer clear
01234567891011121314
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
2
10
2
11
2
12
2
13
2
14
2
15
Selector
Edge detection
WS1-0 WPCR:bit 2-1
0
00
Interval time
CL-SUB
CL-SUB
CL-SUB
CL-SUB
2
10
/ F
2
13
/ F
2
14
/ F
2
15
/ F
WIE WPCR:bit 6
0
1
Interrupt disable
Interrupt enable
Clock timer
Interrupt (#49)
1
0
WIF WPCR:bit 7
0
1
Without interrupt request
With interrupt request
WRITE; 0: Flag clear
1
10
11