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Chapter 31 External Bus
11.Bus Arbitration
Figure 11-2 Timing Chart for Acquiring the Bus Right
• Setting 1 for the BREN bit of the TRC register enables bus arbitration by BRQ/BGRNT to be performed.
• When the bus right is released, the pin is set to high impedance and then BGRNT is asserted one cycle later.
• When the bus right is acquired, BGRNT is negated and then each pin is activated one cycle later.
• CSn is set to high impedance only if the SREN bit in the ACR0-7 registers is set.
• If all areas enabled by the CSER register are shared (the SREN bit of the ACR register is 1), AS, BAA, RD,
WE, and WR0-WR3 are set to high impedance.
MCLK
A23 to A0
AS
CSn *
D31 to D16
Read
BRQ
BGRNT
WE
1 cycle