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Chapter 20 Software Watchdog Timer
5.Operation
5.2 Starting the Watchdog Timer and Setting the Watchdog Timer Period
The watchdog timer starts once it first writes data to the RSRR (Reset cause register/Watchdog timer control
register) after the reset (RST). At this time, Bits 1 and 0 (WT1 and WT0 bits) set the watchdog timer interval
time. Only the setting for the interval time executed first after the reset is valid, and the other settings executed
at a later time are invalid.
5.3 Postponing the Generation of a Watchdog Reset
Once watchdog timer is started, it is necessary that the WPR (watchdog reset generation postponement
register) should be written periodically with {A5
H
} and {5A
H
} in this order by software. This operation is used to
set the 1-bit counter for detecting the watchdog reset to “0”.
5.4 Confirming that the Watchdog Reset has been Generated
The 1-bit counter for detecting the watchdog reset is set at the falling edge of the output of the timebase
counter where an interval is set. In addition, if the second falling edge is detected while the 1-bit counter is set,
the request for the setting initialization reset (INIT) is generated as the watchdog reset.
5.5 Temporarily Stopped Watchdog Timer (Automatic Generation Postponement)
The watchdog timer resets the 1-bit counter used for detecting the watchdog reset to “0” as initialization while
CPU program operation is stopped. In this state, the generation of the watchdog reset is postponed. The
states where programs stop running are concretely shown below.
• Sleep
• Stop
• Oscillation stability wait RUN
• Is in break when using the emulator debugger and monitor debugger, only if DSU4 is mounted
• Is in break when using the embedded debug support unit (only if EDSU and EMMODE is enabled)
• Period between the time when executing the INTE command and when executing RETI, only if DSU4 is
mounted
• Step trace trap (break per each command with PS register T flag=“1”), only if DSU4 is mounted
In addition, clearing the timebase counter simultaneously initializes the 1-bit counter used for detecting the
watchdog reset, thus causing the reset timing of the watchdog to be postponed.
5.6 Stopping the Watchdog Timer
Once the watchdog timer is started, the watchdog timer operation cannot be stopped until the initialization
reset (RST) is generated.
The watchdog timer is stopped under these states shown below where the operation initialization reset (RST)
is generated until it is restarted by software.
• Operation initialization reset (RST)
• Setting initialization reset (INIT)
• Oscillation stability wait reset