Filter
Top Products
229
Chapter 16 Clock Supervisor
4.Operation Modes
Figure 4-4 Timing Diagram: Initial settings, sub-clock missing before timeout
PONR
MCLK
SCLK
RC_CLK
OSC_STAB
MSVE
MSEN
SSVE
SSEN
MCLK_STBY
SCLK_STBY
TO_MCLK
TO_SCLK
EXT_RST
EXT_RST_OUT
MCLK_OUT
SCLK_OUT
MCLK_MISSING
SCLK_MISSING
SRST