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Chapter 26 DMA Controller
2.DMA Controller (DMAC) Registers
[Bit 30] PAUS (PAUSe)*: Temporary stop instruction
This bit temporarily stops DMA transfer on the corresponding channel. If this bit is set, DMA transfer is not
performed before this bit is cleared (While DMA is stopped, the DSS bits are 1xx
B
.
If this bit is set before starting, DMA transfer continues to be temporarily stopped.
New transfer requests that occur while this bit is set are accepted, but no transfer starts before this bit is
cleared (See 3.9"Operation from Starting to End/Stopping").
• When reset: Initialized to 0.
• This bit is readable and writable.
[Bit 29] STRG (Software TRiGger): Transfer request
This bit generates a DMA transfer request for the corresponding channel. If 1 is written to this bit, a transfer
request is generated when write operation to the register is completed and transfer on the corresponding
channel is started.
However, if the corresponding channel is not activated, operations on this bit are disabled.
If starting by a write operation to the DMAE bit and a transfer request occurring due to this bit are
simultaneous, the transfer request is enabled and transfer is started. If writing of 1 to the PAUS bit and a
transfer request occurring due to this bit are simultaneous, the transfer request is enabled, but DMA transfer is
not started before 0 is written to the PAUS bit.
• When reset: Initialized to 0.
• The read value is always 0.
• Only a write value of 1 is valid. If 0 is write, operation is not affected.
PAUS Function
0 Enables operation of the corresponding channel DMA (initial value)
1 Temporarily stops DMA on the corresponding channel.
STRG Function
0 Disabled
1 DMA starting request