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Chapter 31 External Bus
10.DMA Access Operation
Reference:
For memory on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O
hold wait cycle is generated. For I/O on the receiving side, a write strobe of two bus cycles extended by the I/
O wait cycle is generated. The I/O hold wait cycle does not affect the write strobe. However, the address and
CS signal are retained until the fly-by bus access cycles end.
10.3 DMA Fly-By Transfer (I/O -> SDRAM/FCRAM)
This section describes the operation of DMA fly - by transfer (I/O device to SDRAM/FCRAM).
■ DMA Fly-By Transfer (I/O -> SDRAM/FCRAM)
Figure 4.10 - 3 shows an operation timing chart assuming TYP3 to TYP0 set to 1000B, AWR set to 0051H, and
IOWR set to 41H.