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Chapter 26 DMA Controller
3.DMA Controller (DMAC) Operation
If edge detection is selected for the external pin start source and a transfer request is detected, the request is
retained within DMAC until the clear conditions are met (when the external pin start source is selected for block,
step, or burst transfer).
If level detection or peripheral interrupt start is selected for the external pin start source, DMAC continues the
transfer until all transfer requests are cleared. When they are cleared, DMAC stops the transfer after one transfer
unit (demand transfer or peripheral interrupt start).
Since peripheral interrupts are handled as level detection, use interrupt clear by DMA to handle the interrupts.
Transfer requests are always accepted while other channel requests are being accepted and transfer performed.
The channel that will be used for transfer is determined for each transfer unit after priority has been checked.
■ Clearing Peripheral Interrupts by DMA
This DMA has a function that clears peripheral interrupts. This function works when peripheral interrupt is
selected as the DMA start source (when IS[4:0]=1xxxx
B
).
Peripheral interrupts are cleared only for the set start sources. That is, only the peripheral functions set by IS[4:0]
are cleared.
The timing for clearing an interrupt depends on the transfer mode (See Section 4."Operation Flowcharts").
• Block/step transfer: If block transfer is selected, a clear signal is generated after one block (step) transfer.
• Burst transfer: If burst transfer is selected, a clear signal is generated after transfer is performed the specified
number of times.
• Demand transfer: Since only start requests from external pins are supported in demand transfer, no clear
signal is generated.
■ Temporary Stopping
DMA transfer is stopped temporary in the following cases:
● Setting of temporary stopping by writing to the control register (Set independently for each
channel or all channels simultaneously)
If temporary stopping is set using the temporary stop bit, transfer on the corresponding channel is stopped until
release of temporary stopping is set again. You can check the DSS bits for temporary stopping.
● NMI/hold suppress level interrupt processing
If an NMI request or an interrupt request with a higher level than the hold suppress level occurs, all channels on
which transfer is in progress are temporarily stopped at the boundary of the transfer unit and the bus right is
returned to give priority to NMI/interrupt processing. Transfer request accepted during NMI/interrupt processing
are retained, initiating a wait for completion of NMI processing.
Channels for which requests are retained restart transfer after NMI/interrupt processing is completed.
■ Operation End/Stopping
The end of DMA transfer is controlled independently for each channel. It is also possible to disable operation for
all channels at once.
● Transfer end
If reloading is disabled, transfer is stopped, "Normal end" is displayed as the end code, and all transfer requests
are disabled after the transfer count register becomes 0 (Clear the DENB bit of DMACA).
If reloading is enabled, the initial value is reloaded, "Normal end" is displayed as the end code, and a wait for
transfer requests starts after the transfer count register becomes 0 (Do not clear the DENB bit of DMACA).