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Chapter 31 External Bus
5.Operation of the Ordinary bus interface
Figure 5-2 Timing Chart for the WRn + Byte Control Type
• Operation of AS, CSn, RD, A31-0, and D31-16 is the same as that described in 5.1 "Basic Timing". WRn is
asserted from the 2nd cycle of the bus access. Negation occurs after the wait cycle of bits W15-W12 of the
AWR register is inserted. The timing of asserting RD and WR0-WR3 can be delayed by one cycle by setting
the W01 bit of the AWR register to 1. However, depending on the internal state, assertion of WR0-WR3 may
not start in the 2nd cycle and may even be delayed if the W01 bit is set to 0. (Operation is the same as that for
WR0-WR3 described in 5.1 "Basic Timing" .)
• WR0-WR3 indicate the byte location expressed with negative logic when they are used for access as the byte
enable signal. Assertion continues from the bus access start cycle to the bus access end cycle and changes
at the same timing as the address timing. The byte location for access is indicated for both read access and
write access.
• For write access, data output to D31-16 starts at the timing at which WRn is asserted. If the areas defined by
TYP3-0=0x0x
B
(WR0-WR3 used) and TYP3-0=0x1x
B
(WRn + byte control) are mixed, be sure to make the
following setting for all areas that will be used. (For details, see the notes).
• Set at least one read -> write idle cycle.
• Set at least one write recovery cycle.
MCLK
AS
CSn *
RD
READ
WR
WR0,WR1
WR2,WR3
W
RITE
A[31:0]
D[31:0]
D[31:0]
WR2,WR3
WR0,WR1