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Chapter 26 DMA Controller
3.DMA Controller (DMAC) Operation
• End of the specified transfer count (DMACA:BLK[3:0] x DMACA:DTC[15:0]) => Normal end
• A transfer stop request from a peripheral circuit or the external pin (DSTP) occurred => Error
• An address error occurred => Error
• A reset occurred => Reset
The transfer stop source is indicated (DSS) and the transfer end interrupt or error interrupt for the end source is
generated.
3.1 Setting a Transfer Request
The following three types of transfer requests are provided to activate DMA transfer:
• External transfer request pin
• Built-in peripheral request
• Software request
Software requests can always be used regardless of the settings of other requests.
■ External Transfer Request Pin
A transfer request is generated by input to the input pin prepared for a channel.
The MB91460 series supports channels 0-3 (DREQ0-3).
If the input is valid at this point, the following sources are selected depending on the settings for the transfer type
and the start source:
● Edge detection
If the transfer type is block, step, or burst transfer, select edge detection:
• Falling edge detection: Set with the transfer source selection register. When IS[4:0] of DMACA=01110
B
.
• Rising edge detection: Set with the transfer source selection register. When IS[4:0] of DMACA=01111
B
.
● Level detection
If the transfer type is demand transfer, select level detection:
• H level detection: Set with the transfer source selection register. When IS[4:0] of DMACA=01110
B
.
• L level detection: Set with the transfer source selection register. When IS[4:0] of DMACA=01111
B
.
■ Built-in Peripheral Request
A transfer request is generated by an interrupt from the built-in peripheral circuit.
For each channel, set the peripheral’s interrupt by which a transfer request is generated (When IS[4:0] of
DMACA=1xxxx.)
The built-in peripheral request cannot be used together with an external transfer request.
Note:
Because an interrupt request used in a transfer request seems like an interrupt request to the CPU, disable
interrupts from the interrupt controller (ICR register).
■ Software Request
A transfer request is generated by writing to the trigger bit of a register (STRG of DMACA).
The software request is independent of the external transfer request pin and built-in peripheral request and can