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Chapter 8 Device State Transition
3.State Transition Diagram
3.5 Oscillation-stabilization-wait Reset
This is the state where the device is stopped. This state is entered upon a setting-initialization reset
(INIT).
All internal circuits are stopped except for clock generation control parts (timebase counter and
device state control parts). All internal clocks are stopped while oscillation circuits and main PLL (if
enabled) are operating.
• High-impedance control of external pins by STOP is cancelled.
• For internal circuits this state outputs operation-initialization reset (RST).
• After configured oscillation-stabilization-wait time has passed the oscillation-stabilization-wait
reset state is entered.
• Upon generation of the setting-initialization reset request by the external INITX pin the setting-
initialization reset state (INIT) is entered.
3.6 Operation-initialization Reset (RST)
This is the state where the program execution is initialized. Upon receipt of the operation-
initialization reset (external RSTX pin or software reset) request or the termination of the oscillation-
stabilization-wait reset (RST) this state is active.
CPU’s program is stopped and program counter is initialized. All peripheral circuits are initialized
except for some peripheral circuits. All internal clocks, oscillation circuits and enabled main PLL are
operating.
• For internal circuits this state asserts operation-initialization reset (RST).
• Upon clear of request of operation-initialization reset (RST) this state transits to the RUN
(normal operation) state and executes the operation-initialization reset sequence. Upon returning
from setting-initialization reset (INIT) this state executes the setting-initialization reset sequence.
• Upon generation of the setting-initialization reset request by the external INITX pin the setting-
initialization reset state (INIT) is entered.
3.7 Setting-initialization Reset (INIT)
This is the state where all settings are initialized. Upon receipt of request of setting-initialization
reset (INIT) this state is active.
CPU’s program is stopped and program counter is initialized. All peripheral circuits are initialized.
Oscillation circuits are operating while the main PLL is stopped. All internal clocks are operating
except while “L” level is input to the external INITX pin.
• For internal circuits this state asserts the setting-initialization reset (INIT) and the operation-
initialization reset (RST).
• Upon clear of the setting-initialization reset (INIT) request this state cancels the setting-
initialization reset state and then enters to the oscillation-stabilization-wait reset. After that it
executes the operation-initialization reset sequence.
3.8 Priority of Each Request of State Transition
In any state, each request of the state transition is subject to the following priority:
[Highest
priority] Request of setting-initialization reset (INIT)
Termination of oscillation-stabilization-wait time (This is generated only in status of
oscillation-stabilization-wait reset and oscillation-stabilization-wait RUN.)
Request of operation-initialization reset (RST)
Request of valid interrupt (This is generated only in RUN, sleep or stop status.)
Request of stop mode (Writing in register) (This is generated only in RUN status.)
[Lowest Request of sleep mode (Writing in register) (This is generated only in RUN status.)
priority]