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Chapter 33 I2C Controller
2.I2C Interface Registers
While this bit is ‘1’ the SCL line will hold an ‘L’ level signal. Writing ‘0’ to this bit clears the setting, releases the
SCL line, and executes transfer of the next byte or a repeated start or stop condition is generated.
Additionally, this bit is cleared if a ‘1’ is written to the SCC bit or the MSS bit is being cleared.
SCC, MSS And INT Bit Competition
Simultaneously writing to the SCC, MSS and INT bits causes a competition to transfer the next byte, to
generate a repeated start condition or to generate a stop condition. In these cases the order of priority is as
follows:
Next byte transfer and stop condition generation.
When ‘0’ is written to the INT bit and ‘0’ is written to the MSS bit, the MSS bit takes priority and a stop
condition is generated.
Next byte transfer and start condition generation.
When ‘0’ is written to the INT bit and ‘1’ is written to the SCC bit, the SCC bit takes priority. A repeated start
condition is generated and the content of the IDAR0 register is sent.
Repeated start condition generation and stop condition generation.
When ‘1’ is written to the SCC bit and ‘0’ to the MSS bit, the MSS bit clearing takes priority. A stop condition is
generated and the interface enters slave mode.