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Chapter 31 External Bus
10.DMA Access Operation
Figure 10-3 Timing Chart for DMA Fly - by Transfer (I/O to SDRAM/FCRAM)
memory
address
DACKn
IORD
DEOPn
DACKn
DEOPn
DREQn
FR30
compatible
mode
Basic
mode
MCLK
AS
CSn
SCAS
A31 to 0
D31 to 0
WRn(SWE)
SRAS
Basic cycle
I/O wait
cycle
I/O hold
wait