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Chapter 6 EIT: Exceptions, Interrupts and Traps
9.Caution
8.6 Coprocessor Absent Trap
If you execute coprocessor instruction for unmounted coprocessor, coprocessor absent trap is generated.
■ Operation
1. The contents of the program status (PS) are saved to the system stack.
2. The address of the instruction that caused the undefined instruction exception is saved to the system stack.
3. The value of the system stack pointer (SSP) is reduced by 8.
4. The value “0” is written to the “S” flag in the condition code register (CCR) in the program status (PS).
5. The value ‘TBR+3E0
H
’ is stored in the program counter (PC).
8.7 Coprocessor Error Trap
If error occurs during the use of coprocessor, coprocessor error trap is generated when you execute
coprocessor instruction in order to operate the coprocessor next time.
■ Operation
1. The contents of the program status (PS) are saved to the system stack.
2. The address of the instruction that caused the undefined instruction exception is saved to the system stack.
3. The value of the system stack pointer (SSP) is reduced by 8.
4. The value “0” is written to the “S” flag in the condition code register (CCR) in the program status (PS).
5. The value ‘TBR+3DC
H
’ is stored in the program counter (PC).
8.8 Operation of RETI Instruction
RETI instruction is the instruction which returns from EIT process routine.
■ Operation
1. Load data from stack indicated by (R15)* to the program counter (PC).
2. Increment R15+4 and store to R15.
3. Load data from stack indicated by (R15)* to the program status (PS).
4. Increment R15+4 and store to R15.
RETI instruction should be executed with S flag “0”.
9. Caution
• Since INTE instruction is used for the Debug Support Unit (DSU), do not use it in any application.
• Delay slot for branch instruction has restrictions on EIT.
See “Chapter 7 Branch Instruction (Page No.129)”.