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Chapter 38 Reload Timer
8.Caution
8. Caution
• Count source select bit (TMCSR.CSL[2:0]) settings not in the table: “100”, “111” are disabled.
If they are set, disable the reload timer operation before resetting the count source select bit.
• Operation mode bit (TMCSR.MOD2) must be set to “0”. If it is set to “1”, disable the reload timer count
operation before resetting it. Also the value written during read/modify/write access may be read.
• Control bits (Count source select, operation mode, reload permission) must not be rewritten during
operation.
If they are set during operation, disable the reload timer count operation before resetting them.
• From activation timing, it takes T cycle for the reload value to be loaded to the down counter. (Cycle = 1/
CLKP, CLKP = peripheral clock)
• About output signal internal connections
• Reload timer TOT0-TOT7 outputs are connected to the PPG0-PPG15 internal trigger inputs.
• Reload timer TOT7 output is connected to the A/D converter 0 trigger input.
• Rewriting of the count clock selection bit (CSL[2:0]), operation mode selection bit (MOD[2:0]), output level
setting bit (OUTL), reload permission bit (RELD), and timer interrupt request permission bit (INTE) should be
done when the reload timer is stopped (TMCSR.CNTE=“0”).
• The internal prescaler should be already set when the timer count permission bit (TMCSR.CNTE) is set to
“1”.
• If interrupt request flag set timing and clear timing overlap, the flag setting will be given priority and the clear
operation will be made invalid.
• When writing to the reload register and the reload timing overlap, the old data will be loaded to the counter.
The new data will be loaded during the next reload timing.
• If the loading and counting of the timer register overlap, the load (reload) operation is given priority.
• If you want to enable the count at the same time as you start the count operation, set both the timer count
permission bit (TMCSR.CNTE) and the software trigger bit (TMCSR.TRG) to “1”.