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Chapter 50 Subclock Calibration Unit
5.Register Description
BIT[0]: INTEN - Interrupt enable
This is the interrupt enable bit corresponding to the INT bit. When this bit is set to 1 and the
INT bit is set by the hardware, the calibration module signals an interrupt to the CPU. The
INT-bit itself is not affected by the INTEN bit and is set by hardware even if interrupts are
disabled (INTEN=0).
BIT[1]: INT - Interrupt
This bit indicates the end of the calibration. When the 32KHz/100kHz timer reaches zero after
the start of calibration, the 4MHz Timer Data Register stores the last 4MHz timer value and
the INT bit is set to 1.
The read-modify-write operation to this bit results in reading 1 and writing 0 to this bit clears
this flag(INT=0). Writing 1 to this bit has no effect.
The interrupt flag INT is not reset by hardware. Therefor it must be reset by software before
starting a new calibration. Otherwise the end of the calibration process is only signalized by
the STRT bit (the INT flag stays 1 also during calibration).
BIT[4]: STRT - Calibration Start
When the STRT bit is set to 1 by the software, the calibration starts. The 32kHz/100kHz
Timer
starts counting down from the value stored in the 32KHz/100kHz Timer Data Register
and the 4
MHz Timer starts counting up from zero.
When the 32KHz/100kHz Timer reaches zero, this bit is reset to 0 by the hardware.
If 0 is written into this bit by the software during the calibration process, the calibration is
immediately stopped. If writing 0 by the software and reset to 0 by the hardware happens at
the same time, the hardware operation supersede the software operation. This means the
calibration is properly completed and the INT bit is set to “1”. Writing 1 to this bit during the
calibration has no effect.
0 interrupt disabled (default)
1 interrupt enabled
0 calibration ongoing / module inactive (default)
1 calibration completed
0 calibration stopped, module switched off (default)
1 start calibration