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Chapter 31 External Bus
2.External Bus Interface Registers
[Bits 2] W02 (Address -> CSn Delay)
The address -> CSn delay setting is made when a certain type of setup is required for the address when CSn
falls or CSn edges are needed for successive accesses to the same chip select area.
Set the address and set the delay from AS output to CS0-CS7 output.
If no delay is selected by setting 0, assertion of CS0-CS7 starts at the same timing that AS is asserted. If, at this
point, successive accesses are made to the same chip select area, assertion of CS0-CS7 without change
between two access operations may continue.
If delay is specified by selecting 1, assertion of CS0-CS7 starts when the external clock memory MCLK output
rises. If, at this point, successive accesses are made to the same chip select area, CS0-CS7 are negated at a
timing between two access operations. If CS delay is selected, one setup cycle is inserted before asserting the
read/write strobe after assertion of the delayed CSn (operation is the same as the CSn ->RD/WE setup setting of
W01).
The address -> CSn delay setting works for DACK signal (basic mode) output to the same area in the same way.
DACK output in basic mode has the same waveforms as those of CS output to the same area.
[Bits 1] W01 (CSn -> RD/WRn Setup Extension Cycle)
The CSn -> RD/WRn setup extension cycle is set to extend the period before the read/write strobe is asserted
after CSn is asserted. At least one setup extension cycle is inserted before the read/write strobe is asserted
after CS is asserted.
If 0 cycle is selected by setting 0, RD/WR0-WR3/WRn are output at the earliest when external clock MCLK output
rises just after CS is asserted. WR0-WR3/WRn may be delayed one cycle or more depending on the internal bus
state.
If 1 cycle is selected by setting 1, RD/WR0-WR3/WRn are always output 1 cycle or more later.
When successive accesses are made within the same chip select area without negating CSn, a setup extension
cycle is not inserted. If a setup extension cycle for determining the address is required, set the W02 bit and insert
the address -> CSn delay. Since CSn is negated for each access operation, the setup extension cycle is
enabled.
If the CSn delay set by W02 is inserted, this setup cycle is always enabled regardless of the setting of the W01
bit.
W02 Address -> CSn delay
0 No delay
1 Delay
W01 CSn -> RD/WRn setup delay cycle
0 0 cycle
1 1 cycle