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Chapter 26 DMA Controller
2.DMA Controller (DMAC) Registers
If the bit is set while DMA transfer start is disabled (when DMAE of DMACR=0, or DENB of DMACA=0), the
setting takes effect when start is enabled.
If the bit is set while DMA transfer is temporarily stopped (DMAH[3:0] of DMACR not equal to 0000
B
or PAUS of
DMACA=1), the setting takes effect when temporary stopping is canceled.
2.1 Control/Status Registers A (DMACA0 to 4)
Control/status registers A (DMACA0 to 4) control the operation of the DMAC channels. There is
a separate register for each channel.
This section describes the configuration and functions of control/status registers A (DMACA0 to
4).
■ Bit Configuration of Control/Status Registers A (DMACA0 to 4)
Figure 2-2"Bit Configuration of Control/Status Registers A (DMACA0 to 4)" shows the bit configuration of control/
status registers A (DMACA0 to 4).
Figure 2-2 Bit Configuration of Control/Status Registers A (DMACA0 to 4)
■ Detailed Bit of Control/Status Registers A (DMACA0 to 4)
The following describes the functions of the bits of control/status registers A (DMACA0 to 4).
[Bit 31] DENB (Dma ENaBle): DMA operation enable bit
This bit, which corresponds to a transfer channel, is used to enable and disable DMA transfer.
The activated channel starts DMA transfer when a transfer request is generated and accepted.
All transfer requests that are generated for a deactivated channel are disabled.
When the transfer on an activated channel reaches the specified count, this bit is set to 0 and transfer stops.
The transfer can be forced to stop by writing 0 to this bit. Be sure to stop a transfer forcibly (0 write) only after
temporarily stopping DMA using the PUAS bit (Bit30 of DMACA). If the transfer is forced to stop without first
temporarily stopping DMA, DMA stops but the transferred data cannot be guaranteed. Check whether DMA is
stopped using the DSS[2:0] bits [Bit18-16 of DMACB].
• If a stop request is accepted during reset: Initialized to 0.
• This bit is readable and writable.
• If the operation of all channels is disabled by Bit15 (DMAE bit) of the DMAC all-channel control register
(DMACR), writing 1 to this bit is disabled and the stopped state is maintained. If the operation is disabled by
the above bit while it is enabled by this bit, 0 is written to this bit and the transfer is stopped (forced stop).
DENB Function
0 Disables operation of DMA on the corresponding channel (initial value).
1 Enables operation of DMA on the corresponding channel.
bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
bit
1514131211109876543210
DENB
BLK[3:0]EIS[3:0]IS[4:0]
STRGPAUS
DTC[15:0]
XXXXXXXXXXXXXXXX
B
Address 000200
H
(ch0)
000208
H
(ch1)
000210
H
(ch2)
000218
H
(ch3)
000220
H
(ch4)
Initial value
000000000000XXXX